(a) Technical Field
The present application is related to a light emitting device and method of fabricating the same, and more particularly, to a light emitting device fabricated by chip on wafer processes with photolithography adopting a technique using a current blocking (CB) layer serving as a hard mask.
(b) Description of Background Art
The typical chip on wafer processes for fabricating a horizontal III-nitride based LED chip includes the following steps: first, the light emitting stacked layers (which typically includes p-type layers, n-type layers, and an active layer made from an inorganic semiconductor material sandwiched between one of the p-type layers and one of the n-type layers) are etched to form a mesa structure (requiring a first photolithography process). Second, a current blocking (CB) layer is formed on one of the upper LED stacked layer, and located underneath a p-side electrode, by wet etching (second photolithography process). Third, an ITO layer is formed to be covering the light emitting stacked layers, and exposing a reserved region for a p-side pad electrode of the p-side electrode and the mesa structure (third photolithography process). Fourth, p, n-side pad electrodes/finger electrodes are formed (fourth photolithography process). Fifth, a passivation layer is deposited over the entire top surface of the horizontal nitride LED chip except p, n-side pad electrodes (fifth photolithography process). Thus, conventional technique for fabricating the horizontal III-nitride based LED chip typically includes at least five separate photolithography processes, in which each time, the photolithography process requires the following individual sub-steps: cleaning and preparation of a photoresist-coated surface, applying and coating a photoresist layer onto a material layer such as by spin coating, performing exposure and developing after prebaking to form a patterned photoresist mask, performing wet or dry etching using the patterned photoresist mask, and removing the remaining patterned photoresist layer. In the above-described first step, the mesa structure etching process can be performed using inductively coupled plasma (ICP) etching to expose the n-type layer, such as a n-GaN layer (forming the n-mesa) upon etching a portion of the p-type layer, such as a p-GaN layer and the active layer (or can be also referred to as multiple quantum wells, MQW). Meanwhile, for the sake of preventing ITO layer pattern shift issues, for example leakage current issues between residue ITO and light emitting stacked layers sidewalls, the subsequent four photolithography processes are required to use the resulting mesa pattern obtained at the completion of the first photolithography process, as alignment reference. As a result, the conventional fabrication method for LED chip can be more time consuming (higher cycle time) and requires relatively high process costs.